





about ASDT

Our services
SoC Design Implementation
• Logical Design Implementation
• Design Planning, Place and Route
• Design Rule Check
• Low Power Design Implementation
SoC DFT Implementation
• DFT Architecture and Methodology
• DFT Mode STA/ SIMULATION
• DFT Vector Generation
• DFT to Gate Equivalence checking
DFM DFY Implementation
• Silicon Soc Validation
• Functional and Reliability Testing
• Parametric yield & Performance Variability
Our Success Story
ASDT Established
• TSMC 12nm AI Neoverse SoC T/0
• ASIC 3DIC TSV ChipⅠ
• S* SLSI 5nm 3DIC Controller Chip
• S* 5nm Automotive V* SoC T/O
• ASIC 3DIC TSV Chip
• ASIC 4nm 5G Network
• S* ASIC 4LPP MPW* Chip
• S* 3nm ARM Ananke( CA55 ) CPUs
• S* 3nm SoC Physical Verification
• Foundry 8nm MV LTV Chip
• Foundry 3nm MPW* LTV Chip
• Foundry 14nm Low Power MPW* LTV Chip
• S* 3nm SoC Physical Verification
• TSMC 6nm Japan C* NPU Hardening
• S* 14nm N* NPU Subsystem
• S* DDI Chip
• ASIC TSMC DDI Chip
• AI Semiconductor Convergence Workforce Training Program with Soongsil University
Collaboration Partners

